Sphinx Verilog Domain

Table Of Contents

Sphinx Verilog Domain

Warning

Documentation for this Sphinx extension is under development. Below you can find basic tests for the extension.

Verilog Domain test

verilog:port

input [0:1] port_name_01;

input port_name_02[0:1];

input [0:1] port_name_03[0:1];

input [0:1] port_name_04[0:1], other_name_04;

input [0:1] other_name_05, port_name_05[0:1];

input [0:1] port_name_06[0:1], other_name_06[0:1];

input [0:1] port_name_07[0:1], other_name_07[0:1];

input [0 : 1] port_name_08[0 : 1], other_name_08[0 : 1];

---

input [CONST/(2 * a)] port_name_12;

input port_name_13[CONST/(2 * a)];

input [CONST/(2 * a)] port_name_14[CONST/(2 * a)];

input [CONST/(2 * a)] port_name_15[CONST/(2 * a)], other_name_15;

input [CONST/(2 * a)] other_name_16, port_name_16[CONST/(2 * a)];

input [CONST/(2 * a)] port_name_17[CONST/(2 * a)], other_name_17[CONST/(2 * a)];

input [CONST/(2*a)] port_name_18[CONST/(2*a)], other_name_18[CONST/(2*a)];

input [CONST /(2 * a)] port_name_19[CONST /(2 * a)], other_name_19[CONST /(2 * a)];

---

input [] port_name_23;

input port_name_24[];

input [] port_name_25[];

input [] port_name_26[], other_name_26;

input [] other_name_27, port_name_27[];

input [] port_name_28[], other_name_28[];

input [] port_name_29[], other_name_29[];

input [] port_name_30[], other_name_30[];

---

input [0:1][2:3] port_name_34;

input port_name_35[0:1][2:3];

input [0:1][2:3] port_name_36[0:1][2:3];

input [0:1][2:3] port_name_37[0:1][2:3], other_name_37;

input [0:1][2:3] other_name_38, port_name_38[0:1][2:3];

input [0:1][2:3] port_name_39[0:1][2:3], other_name_39[0:1][2:3];

input [0:1][2:3] port_name_40[0:1][2:3], other_name_40[0:1][2:3];

input [0 : 1][2 : 3] port_name_41[0 : 1][2 : 3], other_name_41[0 : 1][2 : 3];

---

input [0][CONST/(2 * a) : 4] port_name_45;

input port_name_46[0][CONST/(2 * a) : 4];

input [0][CONST/(2 * a) : 4] port_name_47[0][CONST/(2 * a) : 4];

input [0][CONST/(2 * a) : 4] port_name_48[0][CONST/(2 * a) : 4], other_name_48;

input [0][CONST/(2 * a) : 4] other_name_49, port_name_49[0][CONST/(2 * a) : 4];

input [0][CONST/(2 * a) : 4] port_name_50[0][CONST/(2 * a) : 4], other_name_50[0][CONST/(2 * a) : 4];

input [0][CONST/(2*a) :4] port_name_51[0][CONST/(2*a) :4], other_name_51[0][CONST/(2*a) :4];

input [0][CONST /(2 * a) : 4] port_name_52[0][CONST /(2 * a) : 4], other_name_52[0][CONST /(2 * a) : 4];

---

input [0][CONST/(2 * a)][] port_name_56;

input port_name_57[0][CONST/(2 * a)][];

input [0][CONST/(2 * a)][] port_name_58[0][CONST/(2 * a)][];

input [0][CONST/(2 * a)][] port_name_59[0][CONST/(2 * a)][], other_name_59;

input [0][CONST/(2 * a)][] other_name_60, port_name_60[0][CONST/(2 * a)][];

input [0][CONST/(2 * a)][] port_name_61[0][CONST/(2 * a)][], other_name_61[0][CONST/(2 * a)][];

input [0][CONST/(2*a)][] port_name_62[0][CONST/(2*a)][], other_name_62[0][CONST/(2*a)][];

input [0][CONST /(2 * a)][] port_name_63[0][CONST /(2 * a)][], other_name_63[0][CONST /(2 * a)][];

---

(* $flowmap_level = 1 * 2, attr = 4 *) input wire [DATA_WIDTH - 1:0] a1, b1, c1;

(* $flowmap_level=1 *) input a2;

(* $flowmap_level=1 *) input \esc{aped[]tok()en ;

inout fbmimicbidir;

inout DDRCASB;

inout [width_b-1:0] q_b;

inout wire PACKAGE_PIN;

input DataOut_i;

input clk, kld;

input wire [31:0] a3, b2;

input configupdate;

input dataa, datab, datac, datad;

input cam_enable;

input A1EN;

input clock, reset, req_0, req_1;

input B1EN;

input [7:0] tx_data;

input [SIZE-1:0] state;

input enable;

input in;

input wire I;

input wire [7:0] inp_b;

input wire [WIDTH-1:0] I;

input wire clk;

input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;

input [width_clock-1:0] clk;

input clock;

input clk;

input cl$k, \reset* ;

input data, clk, reset;

input data_in;

input din_0, din_1, sel;

input enable;

input integer a, b;

input m_eth_payload_axis_tready;

input reg [11:0] zero2;

input reg zero1;

input req_3;

input reset;

input signed wire4;

input signed [(B_WIDTH - 1) :0] b;

input wire ci;

input wire S;

input wire D_OUT_0;

input wire S0, S1, S2, S3;

input wire [(DataWidth - 1) :0] wdata_a_i;

input wire [6:0] OPMODE;

input wire [DATA_WIDTH/2-1:0] b;

input wire [NBITS-1:0] I1;

input wire wrclk;

output reg [31:0] sum;

output CO;

output clk_out;

output rx_empty;

output y;

output clk_out;

output data_out_ack;

output out;

output parity_out;

output reg out;

output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;

output [15:0] decoder_out;

output [3:0] binary_out;

output [7 : 0] count;

output [7:0] count;

output [7:0] rx_data;

output [WIDTHA+WIDTHB-1:0] RES;

output [Y_WIDTH-1:0] X, Y, CO;

output [number_of_channels-1:0] dataout;

output gnt_0;

output q, \q~ ;

output reg fs_ce;

output reg [WIDTH-1:0] out;

output reg Q0, Q1, Q2, Q3;

output reg [7:0] x, y, z, w;

output reg carry_out, borrow_out, parity_out;

output reg wfi_insn_o;

output reg [WIDTH-1:0] POUT;

output sbox_decrypt_o;

output signed [SIZEOUT-1:0] REF_accum_out, accum_out;

output wand Y;

output wand [3:0] Y;

output wire CARRYCASCOUT;

output wire CIN;

output wire [(DataWidth - 1) :0] rdata_a_o;

output wire [0:(PMPNumChan - 1)] pmp_req_err_o;

output wire [3:0] CARRYOUT;

output wire [DATA_WIDTH-1:0] cout;

output wire [NBITS-1:0] O;

output wire wrclk;

output wire [WIDTH-1:0] POUT;

output wor X;

output wor [3:0] X;

verilog:parameter

parameter param_name_01;

localparam logic param_name_02;

parameter byte param_name_03;

parameter byte param_name_04 = “4”;

parameter logic param_name_05 = 1, param_name_05_b = 2;

parameter [4:0] param_name_06 = 1`b1;

verilog:module

module module_test();

ANSI style

module ansi_top(input wire i_clk, input wire i_inp, output reg o_out);

References: ansi_top i_clk i_inp o_out

module ansi_style_1(input x);

References: ansi_style_1 x

module ansi_style_2(input x, output y);

References: ansi_style_2 x y

module ansi_style_3(wire x);

References: ansi_style_3 x

module ansi_style_4(output signed x);

References: ansi_style_4 x

module ansi_style_5(output signed x = 1);

References: ansi_style_5 x

module ansi_style_6(input x = 0, output y = 2*2);

References: ansi_style_6 x y

module ansi_style_7(inout integer x);

References: ansi_style_7 x

module ansi_style_8(output [7:0] x);

References: ansi_style_8 x

module ansi_style_9(input signed [7:0] x);

References: ansi_style_9 x

module ansi_style_10([7:0] x);

References: ansi_style_10 x

module ansi_style_11([7:0] x, input y);

References: ansi_style_11 x y

module ansi_style_12((* attr *) output integer x);

References: ansi_style_12 x

module ansi_style_13((* attr *) output integer x,(* attr_other *) input [3:0] y);

References: ansi_style_13 x y

module ansi_style_14((* attr *) output integer [7:0] x,(* other, attr *) wire y);

References: ansi_style_14 x y

module ansi_style_15(ref [7:0] x, y);

References: ansi_style_15 x y

module ansi_style_16(ref x[7:0], y);

References: ansi_style_16 x y

module ansi_style_17(ref [7:0] x[7:0], y);

References: ansi_style_17 x y

module ansi_style_18(input .ext1(x[7:4]), input .ext2(x[3:0]), inout y, output .ext3(z));

References: ansi_style_18 x y z

module ansi_style_19(input [7:0] a, input signed [7:0] b, c, d, output [7:0] e, output var signed [7:0] f, g, output signed [7:0] h);

References: ansi_style_19 a b c d e f g h

Non-ANSI style

(* attr = 2 * 2 *) module test1(a, b, c, d, e, f, g, h);

module test2(a, b, c, d, e, f, g, h);

module complex_ports({c, d}, .e(f));

module split_ports(a[7:4], a[3:0]);

module same_port(.a(i), .b(i));

module renamed_concat(.a({b, c}), f, .g(h[1]));

module same_input(a, a);

module mixed_direction(.p({a, e}));

Module parameters

(* x=1 *) module non_ansi_params_test_1#()(port_name);

References: non_ansi_params_test_1

(* x=1 *) module ansi_params_test_1#()(input port_name);

References: ansi_params_test_1

(* x=1 *) module non_ansi_params_test_2#(num = 3, other_num = 2 * 2)(port_name);

References: non_ansi_params_test_2, num, other_num

(* x=1 *) module ansi_params_test_2#(num = 3, other_num = 2 * 2)(input port_name);

References: ansi_params_test_2, num, other_num

(* x=1 *) module non_ansi_params_test_3#(num, other_num)(port_name);

References: non_ansi_params_test_3, num, other_num

Parameter other_num is explicitly described below. The declaration in module header should link to it.

parameter other_num = 2 * 2;

Parameter description.

(* x=1 *) module ansi_params_test_3#(num, other_num)(input port_name);

References: ansi_params_test_3, num, other_num

Parameter other_num is explicitly described below. The declaration in module header should link to it.

parameter other_num = 2 * 2;

Parameter description.

(* x=1 *) module non_ansi_params_test_4#(parameter num = 3, other_num = 2 * 2)(port_name);

References: non_ansi_params_test_4, num, other_num

(* x=1 *) module non_ansi_params_test_5#(parameter num = 3, localparam other_num = 2 * 2, yet_another_one = 42)(port_name);

References: non_ansi_params_test_5, num, other_num yet_another_one

Parameter num is explicitly described below. The declaration in module header should link to it.

parameter num;

Parameter description.

(* x=1 *) module non_ansi_params_test_6#(parameter num = 3, localparam other_num, yet_another_one = 42)(port_name);

References: non_ansi_params_test_6, num, other_num yet_another_one

Nesting and refs

• Top1.a - should link to Top1.a port declaration

• Top1.Nested1.a - should link to Top1.Nested1.a port declaration

• Nested1.a - shouldn’t create a link (symbol does not exist in this scope)

• InOtherFile.p - should link to InOtherFile.p port declaration which is located in another file

• NestTest - should link to NestTest, not to nesttest

• nesttest - should link to nesttest, not to NestTest

• $root - shouldn’t create a link

• Top1.$root - shouldn’t create a link (invalid qualified name)

module a(p);

module Top1(a, b, c);

a and b in the module declaration should link to following port declarations. c shouldn’t be a link.

input a;

input b;

Following port is a duplicate - the module shouldn’t link to it in its ports list.

output b;

Duplicated name test: created link target should be unique (compare with previous b declaration)

module \35(4p3|) (z);

module Nested1(a, b, c);

a and b in the module declaration should link to following port declarations. c shouldn’t be a link. Note that b has :refname: set as it not normally referencable by b

input a;

module InPortsContent1(a);

a in the module declaration shouldn’t be a link.

This module is located inside input a’s ReST directive’s content. However, it should be registered directly in module Nested1 scope.

input b;

Refs test:

• a, Nested1.a, Top1.Nested1.a - should link to Top1.Nested1.a port declaration

• $root.a - should link to a module declaration in toplevel scope

• b, Nested1.b, Top1.Nested1.b - should link to Top1.Nested1 module declaration. The module declares the port in its ports list, and no other declaration is available.

• c, Top1.c - should link to Top1 module declaration.

• Top1.a - should link to Top1.a port declaration

• Top2.a - should link to Top2.a port declaration

• module_escaped (ref used in .rst is module_escaped) - should link to Top1.\35(4p3|) module declaration (the declaration has refname)

• \35(4p3|) - shouldn’t create a link (Top1.\35(4p3|) has refname specified)

• LoremIpsumDolorSitAmetNestTest - shouldn’t create a link (symbol does not exist)

• unique_port_name_in_nest_test - shouldn’t create a link (symbol does not exist in this scope)

input \refname-use , \with-multiple-names ;

refname_use_with_multiple_names (refname_use_with_multiple_names) should refer to port definition above

module Top2(a, b);

a in the module declaration should link to following port declaration. b shouldn’t be a link.

input a;

module Top3(x, y, unique_port_name_in_nest_test);

y in the module declaration should link to following port declaration. x and unique_port_name_in_nest_test shouldn’t be a link.

input y;

input nesttest0, nesttest;

input NestTest, NestTest2;

---

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Cross-document refs

module InOtherFile(p);

input p;

---

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• Praesent

• faucibus

• tortor

• eu

• euismod

• imperdiet.

• Mauris

• a

• porta

• mauris,

• ac

• faucibus

• magna.

• Aliquam

• lacinia

• hendrerit

• interdum.

• Nullam

• tempor,

• massa

• ac

• scelerisque

• porta,

• nunc

• nunc

• dignissim

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• id

• commodo

• ligula

• lorem

• sit

• amet

• ligula.

• Morbi

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• et

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• ut

• euismod.

• In

• eu

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• lectus,

• tempor

• vulputate

• risus.

• Proin

• imperdiet

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• condimentum.

• Nunc

• ultrices

• laoreet

• faucibus.

• Morbi

• fringilla

• efficitur

• dolor,

• et

• eleifend

• erat

• pellentesque

• at.

• Donec

• sed

• ligula

• ac

• ligula

• consequat

• lobortis.

• Integer

• nec

• diam

• id

• magna

• scelerisque

• placerat.

verilog:namespace{,-push,-pop}

• $root::in_global_ns

• $root::A::B::inside_a_b

• $root::A::B::C::D::inside_a_b_c_d

• $root::A::B::inside_a_b_again

• $root::A::B::refname_inside_a_b

• $root::A::B::X::Y::inside_a_b_x_y

• $root::A::namespaces_test_module_in_a

• $root::B::C::D::module_inside_b_c_d

• $root::A::input_in_a

• $root::global_ns_again

input in_global_ns;

.. verilog:namespace:: A::B

input inside_a_b;

.. verilog:namespace-push:: C::D

input inside_a_b_c_d;

.. verilog:namespace-pop::

input inside_a_b_again;

input inside_a_b_with_refname;

.. verilog:namespace-push:: X::Y

input inside_a_b_x_y;

.. verilog:namespace:: A

module namespaces_test_module_in_a(a);

.. verilog:namespace:: B::C
.. verilog:namespace-push:: D

module module_inside_b_c_d(a);

Namespace changes applied inside a directive’s content (e.g. in module description above) should not be propagated to a parent rst scope.

input input_in_a;

.. verilog:namespace::

input global_ns_again;

Symbolator compatibility test

module sincos(cos_z0, sin_z0, done, z0, start, clock, reset);

sincos symbolic view

Sine and cosine computer. Source

This module computes the sine and cosine of an input angle. The floating point numbers are represented as integers by scaling them up with a factor corresponding to the number of bits after the point.

output signed [19:0] cos_z0;

reg signed [19:0] cos_z0;

cosine of the input angle

output signed [19:0] sin_z0;

reg signed [19:0] sin_z0;

sine of the input angle

output done;

reg done;

output flag indicated completion of the computation

input signed [19:0] z0;

input angle

input start;

input that starts the computation on a posedge

input clock;

clock input

input reset;

reset input

Verilog Diagrams compatibility test

module CARRY4(CO, O, CI, CYINIT, DI, S);

Source code without license:

module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
  assign O = S ^ {CO[2:0], CI | CYINIT};
  assign CO[0] = S[0] ? CI | CYINIT : DI[0];
  assign CO[1] = S[1] ? CO[0] : DI[1];
  assign CO[2] = S[2] ? CO[1] : DI[2];
  assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule

Diagram:

---

module d(cos_z0, sin_z0, done, z0, start, clock, reset);

Sine and cosine computer. Source

This module computes the sine and cosine of an input angle. The floating point numbers are represented as integers by scaling them up with a factor corresponding to the number of bits after the point.

output signed [19:0] cos_z0;

reg signed [19:0] cos_z0;

cosine of the input angle

output signed [19:0] sin_z0;

reg signed [19:0] sin_z0;

sine of the input angle

output done;

reg done;

output flag indicated completion of the computation

input signed [19:0] z0;

input angle

input start;

input that starts the computation on a posedge

input clock;

clock input

input reset;

reset input

Indices and tables

• Index

• Module Index

• Search Page

Table Of Contents

Tests

• Verilog Domain test
  • verilog:port
  • verilog:parameter
  • verilog:module
  • Nesting and refs
  • Cross-document refs
  • verilog:namespace{,-push,-pop}
  • Symbolator compatibility test
  • Verilog Diagrams compatibility test