Sphinx Verilog Domain

Table Of Contents

verilog:module

module module_test();

ANSI style

module ansi_top(input wire i_clk, input wire i_inp, output reg o_out);

References: ansi_top i_clk i_inp o_out

module ansi_style_1(input x);

References: ansi_style_1 x

module ansi_style_2(input x, output y);

References: ansi_style_2 x y

module ansi_style_3(wire x);

References: ansi_style_3 x

module ansi_style_4(output signed x);

References: ansi_style_4 x

module ansi_style_5(output signed x = 1);

References: ansi_style_5 x

module ansi_style_6(input x = 0, output y = 2*2);

References: ansi_style_6 x y

module ansi_style_7(inout integer x);

References: ansi_style_7 x

module ansi_style_8(output [7:0] x);

References: ansi_style_8 x

module ansi_style_9(input signed [7:0] x);

References: ansi_style_9 x

module ansi_style_10([7:0] x);

References: ansi_style_10 x

module ansi_style_11([7:0] x, input y);

References: ansi_style_11 x y

module ansi_style_12((* attr *) output integer x);

References: ansi_style_12 x

module ansi_style_13((* attr *) output integer x,(* attr_other *) input [3:0] y);

References: ansi_style_13 x y

module ansi_style_14((* attr *) output integer [7:0] x,(* other, attr *) wire y);

References: ansi_style_14 x y

module ansi_style_15(ref [7:0] x, y);

References: ansi_style_15 x y

module ansi_style_16(ref x[7:0], y);

References: ansi_style_16 x y

module ansi_style_17(ref [7:0] x[7:0], y);

References: ansi_style_17 x y

module ansi_style_18(input .ext1(x[7:4]), input .ext2(x[3:0]), inout y, output .ext3(z));

References: ansi_style_18 x y z

module ansi_style_19(input [7:0] a, input signed [7:0] b, c, d, output [7:0] e, output var signed [7:0] f, g, output signed [7:0] h);

References: ansi_style_19 a b c d e f g h

Non-ANSI style

(* attr = 2 * 2 *) module test1(a, b, c, d, e, f, g, h);

module test2(a, b, c, d, e, f, g, h);

module complex_ports({c, d}, .e(f));

module split_ports(a[7:4], a[3:0]);

module same_port(.a(i), .b(i));

module renamed_concat(.a({b, c}), f, .g(h[1]));

module same_input(a, a);

module mixed_direction(.p({a, e}));

Module parameters

(* x=1 *) module non_ansi_params_test_1#()(port_name);

References: non_ansi_params_test_1

(* x=1 *) module ansi_params_test_1#()(input port_name);

References: ansi_params_test_1

(* x=1 *) module non_ansi_params_test_2#(num = 3, other_num = 2 * 2)(port_name);

References: non_ansi_params_test_2, num, other_num

(* x=1 *) module ansi_params_test_2#(num = 3, other_num = 2 * 2)(input port_name);

References: ansi_params_test_2, num, other_num

(* x=1 *) module non_ansi_params_test_3#(num, other_num)(port_name);

References: non_ansi_params_test_3, num, other_num

Parameter other_num is explicitly described below. The declaration in module header should link to it.

parameter other_num = 2 * 2;

Parameter description.

(* x=1 *) module ansi_params_test_3#(num, other_num)(input port_name);

References: ansi_params_test_3, num, other_num

Parameter other_num is explicitly described below. The declaration in module header should link to it.

parameter other_num = 2 * 2;

Parameter description.

(* x=1 *) module non_ansi_params_test_4#(parameter num = 3, other_num = 2 * 2)(port_name);

References: non_ansi_params_test_4, num, other_num

(* x=1 *) module non_ansi_params_test_5#(parameter num = 3, localparam other_num = 2 * 2, yet_another_one = 42)(port_name);

References: non_ansi_params_test_5, num, other_num yet_another_one

Parameter num is explicitly described below. The declaration in module header should link to it.

parameter num;

Parameter description.

(* x=1 *) module non_ansi_params_test_6#(parameter num = 3, localparam other_num, yet_another_one = 42)(port_name);

References: non_ansi_params_test_6, num, other_num yet_another_one

Table Of Contents

• verilog:module
  • ANSI style
  • Non-ANSI style
  • Module parameters

arrow_back

Previous

verilog:parameter

arrow_forward

Next

Nesting and refs