Sphinx Verilog Domain
Sphinx Verilog Domain


input in_global_ns;
.. verilog:namespace:: A::B
input inside_a_b;
.. verilog:namespace-push:: C::D
input inside_a_b_c_d;
.. verilog:namespace-pop::
input inside_a_b_again;
input inside_a_b_with_refname;
.. verilog:namespace-push:: X::Y
input inside_a_b_x_y;
.. verilog:namespace:: A
module namespaces_test_module_in_a(a);
.. verilog:namespace:: B::C
.. verilog:namespace-push:: D
module module_inside_b_c_d(a);

Namespace changes applied inside a directive’s content (e.g. in module description above) should not be propagated to a parent rst scope.

input input_in_a;
.. verilog:namespace::
input global_ns_again;