Sphinx Verilog Domain

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verilog:parameter

parameter param_name_01;

localparam logic param_name_02;

parameter byte param_name_03;

parameter byte param_name_04 = “4”;

parameter logic param_name_05 = 1, param_name_05_b = 2;

parameter [4:0] param_name_06 = 1`b1;

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